Component, for example nmos transistor, with active region with relaxed compression stresses, and fabrication method

ABSTRACT

An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by a trench insulating region. The transistor, active region and trench insulating region are covered by an additional insulating region. A metal contact extends through the additional insulating region to make contact with the trench insulating region. The metal contact may penetrate into the trench insulating region.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application from United StatesApplication for patent Ser. No. 14/300,663 filed Jun. 10, 2014, whichclaims priority from French Application for Patent No. 1355476 filedJun. 13, 2013, the disclosures of which are incorporated by reference.

TECHNICAL FIELD

The invention relates to integrated circuits, and more specifically tothe relaxing of the compression stresses of an active region, forexample that of an NMOS transistor.

BACKGROUND

In an integrated circuit, the transistors are produced in and on asemiconductive active region, for example of silicon, surrounded by anelectrically insulating region, for example a trench filled for examplewith silicon dioxide.

The fact of producing an MOS transistor in an insulating regionintrinsically causes a compression-stressed active region to be obtainedthrough the presence at its periphery of the insulating region. Also,while a compression-stressed active region favors the efficiency of aPMOS transistor, it by contrast causes the efficiency of an NMOStransistor to be degraded, notably in terms of carrier mobility.

Moreover, the production of fast transistors demands small channellengths and widths and the structures generally produced exhibit asignificant density, which leads to active region dimensions that arevery small, even minimal for the technology concerned.

It is therefore extremely difficult, even impossible, to increase thedimensions of the active regions of the NMOS transistors in order torelax their compression stresses, given the density sought for thestructures produced.

SUMMARY

According to one embodiment, it is proposed to reduce the compressionstresses in the active region of a component unfavorably sensitive tothe compression stresses, for example an NMOS transistor, or else anactive resistor, that is to say one formed in an active region whoseresistive value can vary with the compression stresses, and to do sowithout modifying the specifications of the PMOS transistors.

According to one aspect, an integrated circuit is proposed comprising asubstrate and at least one component unfavorably sensitive tocompression stresses, for example an NMOS transistor, arranged at leastpartially in an active region of the substrate limited by an insulatingregion.

According to a general feature of this aspect, said insulating regioncomprises at least one area in which it has two insulating extentsmutually separated by a separation region formed by a part of thesubstrate.

Thus, according to this aspect, a separation wall is produced in theinsulating region, formed by a part of the substrate, in order to absorba part of the stresses generated by the insulating region. Moreover,since this wall is produced in the insulating region, its production istotally transparent for the designer of the integrated circuit since thelatter simply determines the dimensions of the active region and of theinsulating region without worrying about the content of this insulatingregion, that is to say, in this case, the presence of a wall in thisinsulating region. In practice, this wall is mechanically active toallow for an absorption of the stresses, but totally electricallyinactive (floating). Also, the definition of the positioning of thiswall is advantageously performed directly and automatically at the pointof generation of the active region mask without the intervention of thedesigner and without this separation wall interfering with thetransistor for example.

The component unfavorably sensitive to the compression stresses of itsactive region can be an NMOS transistor or else an active resistor, thatis to say one formed in said active region, without these two examplesbeing limiting.

Moreover, an additional insulating region is arranged over thecomponent, the active region and the insulating region, and separatesthe component from the first metallization level. Also, said separationregion or wall is advantageously also covered by said additionalinsulating region.

According to one embodiment, said separation region has a top facesituated substantially at the same level as said top face of the activeregion and emerges in a bottom region of the substrate.

In other words, the depth of this separation wall is substantially equalto the depth of the insulating region.

So as to allow for a more effective relaxing of the compression stressesin the active region, the insulating extent situated closest to saidactive region has a volume less than or equal to that of the insulatingextent furthest away from the active region.

According to one embodiment, said separation region at least partiallysurrounds said active region.

Moreover, according to one embodiment, the gate region of the transistorhas a part extending over the insulating region outside of and at aminimal distance from said area of the insulating region, that is to sayfrom the area containing said separation region or wall.

In practice, not only must this separation region or wall not besituated under the polysilicon line, for example, of the gate region ofthe transistor, so as not to create a spurious transistor, but it mustalso be situated at a minimum distance from this polysilicon line so asto comply with the design rules (design rules manual) of the technologyconcerned and avoid the spurious effects.

As indicated above, an additional insulating region is arranged over thecomponent, the active region and the insulating region, and separatesthe component from the first metallization level. Also, according toanother embodiment, said integrated circuit comprises at least onecontact region passing through said additional insulating region andcontacting at least the top face of a portion of said insulating region,said at least one contact region being formed by at least one materialdifferent from the materials forming said insulating region and saidadditional insulating region.

This contact region can have the form of a wall that can at leastpartially surround said component.

Said at least one material forming the contact region can comprise ametal, for example tungsten, or else polysilicon without these twoexamples being limiting.

In practice, it is observed that producing a contact passing throughsaid additional insulating region and in particular the insulatingbottom layer (known to those skilled in the art by the acronym CESL,standing for Contact Etch Stop Layer) of this additional insulatingregion in order to simply contact the insulating region, even penetratevery slightly into this insulating region by virtue of an overetching,would also make it possible to relax the compression stresses in theactive region of the component. In practice, said at least one material,for example a metal, forming this contact region is generally atension-stressed material.

This contact region, for example metallic, whose positioning is definedon the “contacts” mask, is mechanically active for the relaxing of thestresses but electrically inactive since one of the ends is in contactwith an insulating region.

Also, such a contact region, for example metallic, can for example beproduced on a point of the insulating region where it is not possible,for dimensional regions, to produce a separation wall, the separationwall being produced, for its part, in another point of the insulatingregion.

Thus, a component, for example an NMOS transistor, equipped with aseparation wall and at least one such metallic contact region, has anactive region that is even more relaxed in terms of compressionstresses.

It is however preferable, to further relax the compression stresses, forthe contact region, for example metallic, to penetrate notablydepth-wise into said portion of the insulating region.

Moreover, it is advantageous for said portion of insulating region withwhich said contact comes into contact, for example metallic, or intowhich said contact penetrates, to belong to that of the insulatingextents separated by the separation wall which is situated closest tosaid active region.

Thus, in this embodiment, there is provided the combination of aseparation wall in the insulating region and of a contact, for examplemetallic, coming at least into contact with, even penetrating into, theinsulating extent situated closest to the active region.

A notable effectiveness in the relaxing of the compression stresses ofthe active region is then obtained.

When the integrated circuit comprises an additional insulating regioncomprising a compressed bottom insulating layer (CESL layer for example)arranged over the component, the active region and the insulatingregion, this compressed bottom insulating layer over the transistor andthe insulating region also contributes to the presence of thecompression stresses in the active region. Also, a relaxing ofcompression stresses in said active region can be obtained by at leastone protuberance arranged over at least a part of said insulating regionand below said compressed bottom insulating layer.

In other words, this protuberance locally raises said compressed bottominsulating layer, which therefore allows for a relaxing of compressionstresses in said active region.

When the component is an NMOS transistor, said protuberanceadvantageously has a structure similar to that of the gate region of thetransistor.

This protuberance can at least partially surround the component, forexample an active resistor.

That said, when the component is an NMOS transistor, the gate region ofwhich has a part extending over the insulating region, this gate regionpart is at least at a minimal distance from said protuberance, so as notto create a spurious structure and to comply with the design rules (DRM)of the technology concerned.

This protuberance, whose positioning is defined on the “poly” mask, ismechanically active for the relaxing of the stresses but electricallyinactive (floating) because it is not electrically connected.

According to another aspect, there is proposed a method for fabricatinga component unfavorably sensitive to compression stresses, for examplean NMOS transistor, comprising a production in a substrate, of aninsulating region limiting an active region of the substrate, and aproduction of the component at least partially in the active region.

According to a general feature of this other aspect, the production ofsaid insulating region comprises, in at least one area of thisinsulating region, a production of two insulating extents mutuallyseparated by a separation region formed by a part of the substrate.

According to one implementation, the production of the two extentscomprises a formation, in the substrate, of two separate trenches and afilling of these trenches by at least one insulating material.

According to one implementation, the definition of the positioning ofsaid two trenches is performed on the active region mask.

According to one implementation, the method also comprises theproduction of an additional insulating region over the component, theactive region and the insulating region, and a production of at leastone contact region, for example metallic, passing through saidadditional insulating region and contacting at least the top face of aportion of said insulating region, said at least one contact regionbeing formed by at least one material different from the materialsforming said insulating region and said additional insulating region.

According to another implementation, the method also comprises aproduction, over the component, the active region and the insulatingregion, of an additional insulating region comprising a compressedbottom insulating layer and a production of at least one protuberanceover at least a part of said insulating region and under said compressedbottom insulating layer.

When the component is an NMOS transistor, said protuberance has astructure similar to that of the gate region of the transistor and isproduced at the same time as said gate region.

According to another aspect, there is proposed a use of at least oneseparation region formed by a part of a substrate incorporating anactive region of a component unfavorably sensitive to compressionstresses in said active region, to separate into two insulating extentsat least a part of an insulating region limiting said active region toobtain a relaxing of compression stresses in said active region.

According to another aspect, there is proposed a use of at least oneseparation region formed by a part of a substrate incorporating anactive region of a component unfavorably sensitive to compressionstresses in said active region, to separate into two insulating extentsat least a part of an insulating region limiting said active region, andof at least one contact region, for example metallic, passing through anadditional insulating region arranged over the component, the activeregion and the insulating region, formed by at least one materialdifferent from the materials forming said insulating region and saidadditional insulating region, and contacting at least the top face of aportion of said insulating region, to obtain a relaxing of compressionstresses in said active region.

According to another aspect, there is proposed a use of at least oneseparation region formed by a part of a substrate incorporating anactive region of a component unfavorably sensitive to compressionstresses in said active region, to separate into two insulating extentsat least a part of an insulating region limiting said active region, ofat least one contact region passing through an additional insulatingregion comprising a compressed bottom insulating layer arranged over thecomponent, the active region and the insulating region and comprising acompressed bottom insulating layer, formed by at least one materialdifferent from the materials forming said insulating region and saidadditional insulating region, and contacting at least the top face of aportion of said insulating region and of at least one protuberancearranged over at least a part of said insulating region and under saidcompressed bottom insulating layer, to obtain a relaxing of compressionstresses in said active region.

In an embodiment, an integrated circuit comprises: a substrate includingan active region delimited by a trench insulating region; a componentunfavorably sensitive to stress arranged at least partially in theactive region; an additional insulating region arranged over thecomponent, the active region and the trench insulating region; and acontact region passing through said additional insulating region andcontacting at least a top surface face of a portion of said trenchinsulating region; wherein said contact region is formed by at least onematerial different from a material forming said trench insulating regionand said additional insulating region.

In an embodiment, a method relaxing of stress in an active region of asubstrate supporting a component unfavorably sensitive to stress,comprises: forming a trench insulating region around the active region;forming an additional insulating region arranged over the component, theactive region and the insulating region; forming a contact regionpassing through said additional insulating region to reach said trenchinsulating region; wherein the contact region is formed by at least onematerial different from materials forming said insulating region andsaid additional insulating region.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and features of the invention will become apparent onstudying the detailed description of non-limiting embodiments andimplementations, and the appended drawings in which:

FIG. 1 schematically illustrates an NMOS transistor of the prior art,

FIG. 2 illustrates an embodiment of an NMOS transistor,

FIG. 3 schematically illustrates a production of an insulating regionaccording to the prior art,

FIG. 4 illustrates an implementation of a method for producing aninsulating region, and

FIGS. 5 to 13 schematically illustrate other embodiments of anintegrated circuit.

DETAILED DESCRIPTION OF THE DRAWINGS

Throughout the following text, the component unfavorably sensitive tocompression stresses is an NMOS transistor.

FIG. 1, the reference TRN designates an NMOS transistor whose activeregion 10 is situated in a semiconductive substrate 1, for example ofsilicon. The active region is surrounded by an insulating region 2, forexample of trench type.

The transistor TRN, forming part of an integrated circuit CI,conventionally comprises a gate region 3. Moreover, the gate region 3,the active region 10 and the insulating region 2 are covered by anadditional insulating region 4 conventionally comprising an insulatingbottom layer 40, for example of silicon nitride, also referred to bythose skilled in the art by the acronym CESL (Contact Etch Stop Layer).The additional insulating region 4 also comprises at least one otherlayer over the layer 40, for example at least one layer 42 of silicondioxide.

The transistor TRN is produced here in a 90 nanometer technology and thedistance D between the gate region 3 and the insulating region 2, thatis to say the length of the source or drain region, is here equal to0.15 micrometers.

Compared to the transistor TRN of FIG. 1, the transistor TRN accordingto the embodiment illustrated in FIG. 2 comprises, in the insulatingregion 2, a separation region 11, formed by a part of the substrate 1,and separating the insulating region 2 into two insulating extents 20and 21.

The separation region is also covered by said additional insulatingregion 4.

Moreover, the top face of the separation wall 11 is situatedsubstantially at the same level as the top face of the active region 10and this separation wall emerges in the bottom part of the substrate 1.The width LG1 of the separation region 11 is here equal to the criticaldimension CD of the technology considered, in this case 0.11micrometers. This critical dimension is the minimum dimension of anactive region line.

The width LG2 of the insulating extent 20 is here equal to the minimumspacing between two active regions defined by the design rules (DesignRules Manual DRM) of the technology concerned, in this case 0.14micrometers for a 90 nanometer technology.

This separation region absorbs the stresses produced by the insulatingextent 21 and, because of this, the stresses in the active region 10result essentially only from the insulating extent 20 which has areduced volume compared to the overall volume of the insulating region 2in the prior art configuration illustrated in FIG. 1.

Thus, this embodiment of FIG. 2 makes it possible to obtain a mobilitygain of 20% compared to a conventional prior art transistor TRN such asthat illustrated in FIG. 1.

FIG. 3 schematically illustrates the production of the insulating region2 delimiting the active area 10 of the transistor TRN of FIG. 1.

A bilayer 70 (silicon oxide/silicon nitride) is deposited on thesubstrate 1, topped by a layer of photosensitive resin 71 that isexposed to light through a mask MSK called “active mask” or “activeregion mask”, which will make it possible to determine the outlines ofthe insulating region 2 and consequently those of the active region.Then, after the resin has been developed, the bilayer 70 and thesubstrate 1 are etched using the remaining part of the resin 71 as hardmask so as to obtain a trench 6 which will be filled with insulatingmaterial so as to form the insulating region 2 of the transistor TRN.

Compared to this prior art, the method according to one implementationof the invention provides (FIG. 4) for defining, in the active mask MSK,the positions of the two insulating extents separated by the separationregion (separation wall). More specifically, after the resin 71 has beenexposed to light and developed, there remain, on the bilayer 70, blocksof resin which will be used as hard masks for the production of twotrenches 60 and 61 in the bilayer 70 and the substrate 1. These twotrenches are de facto separated by the separation wall 11 and will befilled with the insulating material to produce the two insulatingextents 20 and 21 of the transistor of FIG. 2.

It will be noted here that the trenches 60 and 61 are situated withinthe outline of the insulating region 6.

Also, it is this outline which is defined by the designer when definingthe dimension of the active regions. Consequently, the fact ofproviding, in the mask MSK, two trenches in this insulating region istotally transparent to the designer, and all the more so since theseparation wall 11 is electrically inactive.

The defining of these trenches is advantageously performed automaticallyin the generation of the active mask by taking account of differentdimensions which will be returned to in more detail hereinbelow.

The integrated circuit CI illustrated in FIG. 5 comprises two NMOStransistors TRNA, TRNB. The transistor TRNA comprises an active region10A surrounded by the insulating region 2 and the transistor TRNBcomprises the active region 10B also surrounded by the insulating region2.

The transistor TRNA comprises a gate region 3A formed, for example, by apolysilicon line. This gate region 3A comprises a part 30A situated overthe active region 10A, a part 31A extending beyond a first end of theactive region and allowing for a contact on the gate region and anotherpart 32A extending beyond the second end of the active region.

The gate region 3B of the transistor TRNB has a structure similar to thegate region 3A. More specifically, it comprises a central part 30Bsituated over the active region 10B and two parts 31B and 32B extendingbeyond this active region 10B.

The area 8 represents the N+ implantation area of the two NMOStransistors. Elsewhere it can be seen that the integrated circuit CIcomprises, around the two transistors TRNA and TRNB, a separation region11 formed in the insulating region 2 and separating the latter intoseveral pairs of insulating extents 20, 21.

In this embodiment, the space ESP between the two active regions 10A and10B is not sufficient to allow for the formation of a separation regionbetween these two active regions. In practice, this space has to be atleast equal to two times the minimum gap LG2 between two active regionsplus the critical dimension LG1, i.e. 0.39 micrometer for a 90 nanometertechnology.

Moreover, the parts 31A, 32A, 31B and 32B of the gate regions 3A and 3Bare situated outside the area in which the separation region 11 issituated.

More specifically, these parts do not overlap a part of the separationwall 11 so as not to form a spurious transistor, and the distance D3between an end of the separation region 11 and a gate region part, forexample the part 32A, must be greater than a minimum distance, forexample 0.05 micrometers in the technology concerned, in this case the90 nanometer technology.

Thus, the dimensions LG1, LG2, D3 and ESP are used automatically in thecomputer tool for generating the active mask to determine, as a functionof the positions of the different active regions 10 and insulatingregions 2, the possible locations of the separation wall or walls inthese insulating regions and the geometries and dimensions of the orthese separation wall(s).

And this is done automatically without the intervention of the circuitdesigner and totally transparently for said designer.

In the embodiments illustrated in FIGS. 6 and 7, the relaxing of thestresses in the active region 10 of the transistor TRN is obtained by ametallic contact 9 passing through the additional insulating region 4 soas to, in the present case, penetrate into the insulating region 2.

That said, it is observed that even if the metallic contact 9 passesonly through the insulating region 4, and notably the CESL layer 40,without penetrating into the insulating region 2, as illustrated inFIGS. 8 and 9, a relaxing of the compression stresses is neverthelessobtained in the active region 10 of the transistor TRN compared to thecompression stresses of the region 10 of the transistor TRN of FIG. 1.

And this holds true whether the layer 40 is a compressed layer or atension layer because, in the latter case, the material used for thecontact region 9 is generally a material that is itself tensioned. Also,the inventors have observed that the combination of a tensioned layer 40passed through by a contact region which is itself tensioned made itpossible to increase the tension in the channel region which makes itpossible to increase the mobility of the electrons.

As an indication, such an embodiment (FIGS. 8 and 9) makes it possibleto obtain a mobility gain of 20% compared to a transistor TRN of theprior art such as that illustrated in FIG. 1. The mobility gain isgreater for the embodiment of FIGS. 6 and 7 and depends on the depth ofpenetration of the contact 9 into the insulating region 2.

Such a metallic contact 9 is produced in a way similar to the metalliccontacts intended to contact the source, drain and gate regions of thetransistor to link them to a metallization level of the interconnectpart (BEOL: Back End Of Lines) of the integrated circuit.

That said, this metallic contact 9, whose positioning is defined on the“contacts” mask, and whose geometry can be different from that of theconventional contacts intended to contact the source, drain and gateregions, is mechanically active for the relaxing of these stresses, butelectrically inactive since one of the ends is in contact with aninsulating region.

The use of metallic contacts coming into contact with the insulatingregion 2, even penetrating into this insulating region 2, isparticularly advantageously when the space between two active regions oftwo NMOS transistors is not sufficient to produce a separation wall 11.In practice, the dimensional constraints to be observed to produce ametallic contact are less strict than those governing the production ofa separation wall 11.

Thus, in the 90 nm technology for example, the minimum width D2 of acontact region 9 is equal to 0.12 micrometer and the minimum distance D1between a contact region 9 and the active region edge is equal to 0.10micrometers.

By analogy with the generation of the active mask, the dimensions D1 andD2 are used automatically in the computer tool for generating the“contacts” mask to determine, as a function of the positions of thedifferent active regions 10 and insulating regions 2, the possiblelocations of the contact region or regions 9 contacting or penetratinginto these insulating regions as well as the geometries and dimensionsof the or these contact region(s).

And here again, this is done automatically without the intervention ofthe circuit designer and totally transparently for said designer.

A configuration combining separation wall 11 and contact wall 9 is veryschematically illustrated notably in FIG. 10.

In this FIG. 10, the two active regions 10A and 10B of two NMOStransistors are separated by a space ESP that is insufficient to producea separation wall 11. In this case, a metallic contact 9 is produced,extending between the two active regions 10A and 10B, and either cominginto contact with the insulating region 2 or penetrating into thisinsulating region.

Moreover, it is possible, in combination, as illustrated in FIG. 10, toproduce, around the remaining part of the active region 10B, aseparation wall 11 in the insulation region 2 so as to define twoinsulating extents 20 and 21.

Whereas in the embodiment of FIGS. 6 to 10 the contact, for examplemetallic, came into contact with the insulating region 2 or penetratedinto this insulating region 2, the contact, for example metallic, 9, canalso, as illustrated in FIG. 11, come into contact with or penetrateinto one of the two insulating extents 20 and 21 of the insulatingregion 2 separated by the separation wall 11. That said, it ispreferable for the metallic contact to come into contact with theinsulating extent 20 situated closest to the active region 10 so as tomake the relaxing of the stresses in the active region all the moreeffective. Also, as an indication, the mobility gain of a transistor TRNsuch as that illustrated in FIG. 11 is 50% compared to the transistorTRN of FIG. 1.

In the embodiments illustrated in FIGS. 12 and 13, the bottom insulatinglayer 40 is a compression-stressed layer. And the relaxing of thestresses in the active region 10 of the transistor TRN is obtained by aprotuberance 12 resting on the insulating region and situated under thebottom insulating layer 40.

In other words, this protuberance locally raises the bottom insulatinglayer 40, which allows for a relaxing of the compression stresses in theactive region 10.

As illustrated in FIG. 12, when the component unfavorably sensitive tocompression stresses is an NMOS transistor TRN, this protuberanceadvantageously has a structure similar to that of the gate region 3 ofthe transistor. This protuberance then comprises, for example,polysilicon in its central part 120.

In the 90 nm technology for example, the minimum width D4 of the centralpart of a protuberance 12 is equal to 0.1 micrometer and the minimumdistance D5 between a central part of a protuberance 12 and the activeregion edge is equal to 0.05 micrometers.

The integrated circuit of FIG. 13 has a structure identical to thatillustrated in FIG. 5.

In this embodiment, the space ESP between the two active regions 10A and10B is not sufficient to allow for the formation of a protuberancebetween these two active regions. In practice, this space must be atleast equal to two times the minimum spacing D5 plus the minimum widthD4, i.e. 0.02 micrometers for a 90 nanometer technology. However, it ispossible to produce a protuberance 12 on the insulating region 2 whichpartially surrounds the two active regions 10A and 10B, but withprecautions that must be taken in the gate regions.

More specifically, the parts 31A, 32A, 31B and 32B of the gate regions3A and 3B are situated over the insulating region, and in such a waythat a protuberance 12 does not form a spurious structure, the distanceD6 between one end of the protuberance 12 and a gate region part, forexample the part 32A, must be greater than a minimum distance, forexample 0.14 micrometers in the technology concerned, in this case the90 nanometer technology.

The production of the protuberance 12 is performed at the same time asthe production of the gate region 3 and with production steps identicalto those used for the production of this gate region.

More specifically, after having produced, by deposition and etching, thecentral part of the gate region 3 and the central part 120 of theprotuberance 12, these central parts of insulating lateral regions orspacers are flanked. Then, the additional insulating region 4 isproduced with the compressed bottom layer 40.

The positioning and the geometry of the central part 120 of polysiliconof the protuberance 12 are defined in the “poly” mask used to define thepositions and geometries of the gate regions of the transistors.

Also, by analogy with the generation of the active mask, the dimensionsD4, D5 and D6 are used automatically in a computer tool for generatingthe “poly” mask to determine, as a function of the positions of thedifferent active regions 10 and insulating regions 2, the possiblelocations of the protuberance or protuberances 12 as well as thegeometries and dimensions of the or these protuberance(s).

And here again, this is done automatically without the intervention ofthe circuit designer and totally transparently for said designer.

Obviously, it is possible to combine separation wall and/or contactregion and/or protuberance in an integrated circuit.

If, for example in the embodiment of FIG. 13, the value of the space ESPbetween the two active regions is less than 2LG2+LG1 (0.39 micrometersin the 90 nanometer technology) and less than 2D1+D2 (0.32 micrometer inthe 90 nanometer technology), then it is not possible to produce at thispoint any separation wall or contact region, but if this space is,however, greater than 2D5+D4 (0.20 micrometers in the 90 nanometertechnology) a protuberance 12 can be inserted between these two activeregions 10A and 10B.

And simply by placing a protuberance 12 between these two activeregions, it would be possible, for example, to replace the peripheryprotuberance 12 of FIG. 13 with a separation wall 11.

What is claimed is:
 1. An integrated circuit, comprising: a substrateincluding an active region delimited by a trench insulating region; acomponent unfavorably sensitive to stress arranged at least partially inthe active region; an additional insulating region arranged over thecomponent, the active region and the trench insulating region; and acontact region passing through said additional insulating region andcontacting at least a top surface face of a portion of said trenchinsulating region; wherein said contact region is formed by at least onematerial different from a material forming said trench insulating regionand said additional insulating region.
 2. The integrated circuitaccording to claim 1, wherein said at least one material of the contactregion comprises a metal.
 3. The integrated circuit according to claim2, wherein the component is a transistor and wherein said metal is asame metal as used for making electrical contact to said transistor. 4.The integrated circuit according to claim 1, wherein the contact regionpenetrates into said portion of said trench insulating region to a depthbelow an upper surface of the substrate.
 5. The integrated circuitaccording to claim 1, wherein said additional insulating regioncomprises an etch stop layer in compressed stress, said contact regionpenetrating through said etch stop layer.
 6. The integrated circuitaccording to claim 1, wherein said additional insulating regioncomprises an etch stop layer in tensile stress, said contact regionpenetrating through said etch stop layer.
 7. The integrated circuitaccording to claim 6, wherein said contact region is also in tensilestress.
 8. The integrated circuit according to claim 1, wherein saidadditional insulating region comprises an etch stop layer, and furthercomprising at least one protuberance arranged over at least a part ofsaid trench insulating region and below said etch stop layer.
 9. Theintegrated circuit according to claim 8, wherein said etch stop layer isin compressed stress.
 10. The integrated circuit according to claim 8,wherein said component is a transistor having a transistor gateincluding a gate electrode and sidewall spacers.
 11. The integratedcircuit according to claim 10, wherein said protuberance has a structuresimilar to that of the transistor gate including an electrode andsidewall spacers.
 12. The integrated circuit according to claim 11,wherein the gate electrode of the transistor gate extends over thetrench insulating region and is spaced from said protuberance.
 13. Theintegrated circuit according to claim 1, further comprising: anadditional active region delimited by the trench insulating region; anadditional component unfavorably sensitive to compression stressesarranged at least partially in the additional active region; whereinsaid trench insulating region comprises at least one area adjacent thesecond active region formed by two insulating extents that are mutuallyseparated by a separation region formed by a part of the substrate. 14.The integrated circuit according to claim 13, wherein said separationregion has a top face situated substantially at a same level as an uppersurface of the additional active region.
 15. The integrated circuitaccording to claim 13, wherein the insulating extent situated closest tosaid additional active region has a cross-sectional area less than orequal to a cross-sectional area of the insulating extent situatedfurther away from the additional active region.
 16. The integratedcircuit according claim 13, wherein said separation region at leastpartially surrounds said additional active region.
 17. The integratedcircuit according to claim 13, wherein said contact region is positionedbetween the active area and the additional active area.
 18. Theintegrated circuit according to claim 13, further comprising: anadditional contact region passing through said additional insulatingregion and contacting at least a top surface face of a portion of saidtrench insulating region; wherein said additional contact region isformed by at least one material different from the material forming saidtrench insulating region and said additional insulating region.
 19. Theintegrated circuit according to claim 18, wherein said at least onematerial of the contact region and additional contact region comprises ametal.
 20. The integrated circuit according to claim 18, wherein theadditional contact region contacts the insulating extent situatedclosest to said additional active region.
 21. The integrated circuitaccording to claim 18, wherein the additional contact region penetratesinto the insulating extent situated closest to said additional activeregion to a depth below an upper surface of the substrate.
 22. Theintegrated circuit according to claim 18, wherein said additionalinsulating region comprises an etch stop layer in compressed stress,said additional contact region penetrating through said etch stop layer.23. The integrated circuit according to claim 18, wherein saidadditional insulating region comprises an etch stop layer in tensilestress, said additional contact region penetrating through said etchstop layer.
 24. The integrated circuit according to claim 23, whereinsaid additional contact region is also in tensile stress.
 25. A methodrelaxing of stress in an active region of a substrate supporting acomponent unfavorably sensitive to stress, comprising: forming a trenchinsulating region around the active region; forming an additionalinsulating region arranged over the component, the active region and theinsulating region; forming a contact region passing through saidadditional insulating region to reach said trench insulating region;wherein the contact region is formed by at least one material differentfrom materials forming said insulating region and said additionalinsulating region.
 26. The method according to claim 25, wherein thecontact region penetrates into said insulating region.
 27. The methodaccording to claim 25, wherein said additional insulating regioncomprises an etch stop layer in compressed stress, said contact regionpenetrating through said etch stop layer.
 28. The method according toclaim 25, wherein said additional insulating region comprises an etchstop layer in tensile stress, said contact region penetrating throughsaid etch stop layer.
 29. The method according to claim 28, wherein saidcontact region is also in tensile stress.
 30. The method according toclaim 25, further comprising: forming at least one protuberance arrangedover at least a part of said trench insulating region and under acompressed bottom insulating layer of said additional insulating region.31. The method according to claim 30, wherein said component is atransistor having a transistor gate including a gate electrode andsidewall spacers, and wherein said protuberance has a structure similarto that of the transistor gate including an electrode and sidewallspacers.